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參數(shù)資料
| 型號： | CY7C43644 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 每1000 x36 x2雙向同步FIFO瓦特/總線匹配（每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配） |
| 文件頁數(shù)： | 27/37頁 |
| 文件大?。?/td> | 581K |
| 代理商： | CY7C43644 |
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CY7C43624
CY7C43634/CY7C43644
CY7C43664/CY7C43684
27
PRELIMINARY
Notes:
48. If Port B is configured for word size, data can be written to the Mail2 register using B
(B
are
“
don
’
t care
”
inputs). In this first case A
0
–
will have
valid data (A
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B
0
–
8
(B
9
–
35
are
“
don
’
t care
”
inputs). In this second case, A
will have valid data (A
9
–
35
will be indeterminate).
49. Retransmit is performed in the same manner for FIFO2.
50. Clocks are free-running in this case.
51. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
RTR
.
52. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
RTR
to update these flags.
Switching Waveforms
(continued)
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B
0
–
35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[48]
FIFO1 Retransmit Timing
ENB
RT1
t
PRT
t
RTR
EFB/FFA
[49, 50, 51, 52]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43664 | 4K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(4K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43684 | 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43636 | 512 x36/x18x2 Tri Bus FIFO(512 x36/x18x2 三路總線 先進(jìn)先出) |
| CY7C43626 | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43644AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 128-Pin TQFP |
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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