參數(shù)資料
型號: CY7C1916BV18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)(2字突發(fā)結(jié)構(gòu),18 -兆位的DDR - II SRAM的)
文件頁數(shù): 11/28頁
文件大?。?/td> 469K
代理商: CY7C1916BV18
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Document Number: 38-05621 Rev. *C
Page 11 of 28
Write Cycle Descriptions
(CY7C1320BV18)
[2, 8]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
2
L
K
K
Comments
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L
L
L
L-H
L
H
H
H
L-H
L
H
H
H
L-H
H
L
H
H
L-H
H
L
H
H
L-H
H
H
L
H
L-H
H
H
L
H
L-H
H
H
H
L
L-H
H
H
H
L
L-H
H
H
H
H
H
H
H
H
L-H
L-H
Write Cycle Descriptions
(CY7C1916BV18)
[2, 8]
BWS
0
L
K
K
Comments
L-H
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is written into the device.
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is written into the device.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L-H
H
H
L-H
L-H
相關(guān)PDF資料
PDF描述
CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
CY7C1316BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
CY7C1318BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
CY7C192 64K x 4 Static RAM with Separate I/O(帶獨立的輸入/輸出口的64K x 4靜態(tài) RAM)
CY7C194B 256 Kb (64K x 4) Static RAM
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CY7C192-25DMB 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 256K-Bit 64K x 4-Bit 25ns 28-Pin CDIP
CY7C192-35VC 制造商:Cypress Semiconductor 功能描述: