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| 型號(hào)： | CY7C1446AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲(chǔ)器（36字節(jié)（100萬(wàn)x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 9/31頁(yè) |
| 文件大?。?/td> | 531K |
| 代理商： | CY7C1446AV33 |
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 9 of 31
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
A1: A0
00
01
10
11
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
01
00
11
10
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
A1: A0
00
01
01
10
10
11
11
00
Second
Address
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
100
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
Add. Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
CE
1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
CE
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
ADSC
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
OE CLK
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
DQ
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Tri-State
D
D
Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
, CE
, and CE
are available only in the TQFP package. BGA package has only 2 chip selects CE
and CE
.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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