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參數(shù)資料
| 型號： | CY7C1446AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲器（36字節(jié)（100萬x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 531K |
| 代理商： | CY7C1446AV33 |
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 15 of 31
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V
DD
= 3.135 to 3.6V unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
Test Conditions
Min.
2.4
2.0
2.9
2.1
Max.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
OH2
Output HIGH Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
[13]
Architecture/Memory Type(23:18)
CY7C1440AV33
(1M x 36)
000
01011
000000
CY7C1442AV33
(2M x 18)
000
01011
000000
CY7C1446AV33
(512K x 72)
000
01011
000000
Description
Describes the version number.
Reserved for Internal Use
Defines memory type and
architecture
Defines width and density
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
100111
00000110100
010111
00000110100
110111
00000110100
ID Register Presence Indicator (0)
1
1
1
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
89
–
Bit Size (x18)
3
1
32
89
–
Bit Size (x72)
3
1
32
–
138
Instruction
Bypass
ID
Boundary Scan Order (165-ball FBGA package)
Boundary Scan Order (209-ball FBGA package)
Identification Codes
Instruction
EXTEST
IDCODE
Code
000
001
Description
Captures the I/O ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
SAMPLE Z
010
RESERVED
011
Notes:
12.All voltages referenced to V
(GND).
13.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1446V33-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 36MBIT 512KX72 3.5NS 100TQFP - Bulk |
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| CY7C144AV-25ACKJ | 制造商:Cypress Semiconductor 功能描述: |
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