- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379075 > CY7C1446AV33 (Cypress Semiconductor Corp.) 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C1446AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲器（36字節(jié)（100萬x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 20/31頁 |
| 文件大?。?/td> | 531K |
| 代理商： | CY7C1446AV33 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 20 of 31
Switching Characteristics
Over the Operating Range
[24, 25]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Description
–250
–200
–167
Unit
ms
Min.
1
Max
Min.
1
Max.
Min.
1
Max
V
DD
(Typical) to the first Access
[20]
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.5
1.5
5
6
ns
ns
ns
2.0
2.0
2.4
2.4
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[21, 22, 23]
Clock to High-Z
[21, 22, 23]
OE LOW to Output Valid
OE LOW to Output Low-Z
[21, 22, 23]
OE HIGH to Output High-Z
[21, 22, 23]
2.6
3.2
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.5
1.3
1.5
1.5
2.6
2.6
3.0
3.0
3.4
3.4
0
0
0
2.6
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
20.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
21.t
, t
,t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
22.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
23.This parameter is sampled and not 100% tested.
24.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
25.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1460AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1464AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1462AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1460AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1464AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1446V33-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 36MBIT 512KX72 3.5NS 100TQFP - Bulk |
| CY7C1447AV25-133BGI | 功能描述:靜態(tài)隨機存取存儲器 36MB (512Kx72) 2.5v 133MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C144AV-20AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 3.3V 64K-Bit 8K x 8 20ns 64-Pin TQFP |
| CY7C144AV-25AC | 功能描述:IC SRAM 64KB DUAL 64-TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C144AV-25ACKJ | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。