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參數(shù)資料
| 型號： | CY7C1446AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲器（36字節(jié)（100萬x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 531K |
| 代理商： | CY7C1446AV33 |
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 13 of 31
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1446V33-167AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 36MBIT 512KX72 3.5NS 100TQFP - Bulk |
| CY7C1447AV25-133BGI | 功能描述:靜態(tài)隨機存取存儲器 36MB (512Kx72) 2.5v 133MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C144AV-20AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 3.3V 64K-Bit 8K x 8 20ns 64-Pin TQFP |
| CY7C144AV-25AC | 功能描述:IC SRAM 64KB DUAL 64-TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C144AV-25ACKJ | 制造商:Cypress Semiconductor 功能描述: |
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