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| 型號(hào)： | CY7C1392BV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 8 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 9/27頁(yè) |
| 文件大?。?/td> | 446K |
| 代理商： | CY7C1392BV18-167BZC |
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CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 9 of 27
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
LD
L
R/W
L
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data
on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
D(A + 0) at K(t + 1)
↑
D(A + 1) at K(t + 1)
↑
L-H
L
H
Q(A + 0) at C(t + 1)
↑
Q(A + 1) at C(t + 2)
↑
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
Write Cycle Descriptions
(CY7C1392BV18 and CY7C1393BV18)
[2, 8]
BWS
0
/NWS
0
L
BWS
1
/NWS
1
L
K
K
-
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1392BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1393BV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1392BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1393BV18
both bytes (D
[17:0]
) are written into the device.
-
During the Data portion of a Write sequence
:
CY7C1392BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1393BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1392BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1393BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1392BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1393BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1392BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1393BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
L
L
-
L
H
L-H
L
H
-
H
L
L-H
H
L
–
H
H
H
H
L-H
–
Notes:
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS
, BWS
in the case of CY7C1392BV18 and CY7C1393BV18 and also
BWS
2
, BWS
3
in the case of CY7C1394BV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
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