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參數(shù)資料

型號：	CY7C1392BV18-167BZC
廠商：	CYPRESS SEMICONDUCTOR CORP
元件分類：	DRAM
英文描述：	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述：	2M X 8 DDR SRAM, 0.5 ns, PBGA165
封裝：	13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)：	7/27頁
文件大小：	446K
代理商：	CY7C1392BV18-167BZC

CY7C1392BV18

CY7C1992BV18

CY7C1393BV18

CY7C1394BV18

Document Number: 38-05623 Rev. *C

Page 7 of 27

Functional Overview

The CY7C1392BV18, CY7C1992BV18, CY7C1393BV18,

CY7C1394BV18 are synchronous pipelined Burst SRAMs

equipped with a DDR-II Separate I/O interface.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing

is referenced to the rising edge of the output clocks, C/C (or

K/K when in single clock mode).

All synchronous data inputs (D

[x:0]

) pass through input

registers controlled by the rising edge of input clocks (K and

K). All synchronous data outputs (Q

[x:0]

) pass through output

registers controlled by the rising edge of the output clocks, C/C

(or K/K when in single clock mode). All synchronous control

(R/W, LD, BWS

[x:0]

) inputs pass through input registers

controlled by the rising edge of the input clock (K).

CY7C1393BV18 is described in the following sections. The

same

basic

descriptions

CY7C1992BV18, and CY7C1394BV18.

apply

CY7C1392BV18,

Read Operations

The CY7C1393BV18 is organized internally as two arrays of

1M x 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

R/W

HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to the Address inputs is

stored in the Read address register. Following the next K clock

rise the corresponding lowest-order 18-bit word of data is

driven onto the Q

[17:0]

using C as the output timing reference.

On the subsequent rising edge of C the next 18-bit data word

is driven onto the Q

[17:0]

. The requested data will be valid

0.45 ns from the rising edge of the output clock (C or C, or K

or K when in single clock mode, for 250-MHz and 200-MHz

devices). Read accesses can be initiated on every K clock

rise. Doing so will pipeline the data flow such that data is trans-

ferred out of the device on every rising edge of the output

clocks, C/C (or K/K when in single clock mode).

When Read access is deselected, the CY7C1393BV18 will

first complete the pending Read transactions. Synchronous

internal circuitry will automatically tri-state the outputs

following the next rising edge of the positive output clock (C).

Write Operations

Write operations are initiated by asserting R/W

LOW and LD

LOW at the rising edge of the positive input clock (K). On the

following K clock rise the data presented to D

[17:0]

is latched

and stored into the lower 18-bit Write Data register provided

BWS

[1:0]

are both asserted active. On the subsequent rising

edge of the negative input clock (K), the information presented

to D

[17:0]

is also stored into the Write Data register provided

BWS

[1:0]

are both asserted active. Write accesses can be

initiated on every rising edge of input clock (K). Doing so

pipelines the data flow so that 18 bits of data are written into

the device on every rising edge of both input clocks (K and K).

Echo Clock

CQ is referenced with respect to C

. This is a free-running clock and is synchronized to the input

clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to

K. The timings for the echo clocks are shown in the AC Timing table.

Output Impedance Matching Input

. This input is used to tune the device outputs to the system

data bus impedance. CQ, CQ, and Q

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a

resistor connected between ZQ and ground. Alternately, this pin can be connected directly to

DDQ

, which enables the minimum impedance mode. This pin cannot be connected directly to

GND or left unconnected.

DLL Turn Off, active LOW

. Connecting this pin to ground will turn off the DLL inside the device. The

timings in the DLL turned off operation will be different from those listed in this data sheet.

TDO for JTAG

TCK pin for JTAG

TDI pin for JTAG

TMS pin for JTAG

Not connected to the die