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參數(shù)資料
| 型號(hào)： | CY7C1306BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM) |
| 中文描述： | 18兆位的2四年防務(wù)審查架構(gòu)（18Mbit，2突發(fā)流水線SRAM的突發(fā)，國防評估報(bào)告結(jié)構(gòu)，流水線的SRAM） |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 821K |
| 代理商： | CY7C1306BV25 |
18-Mbit Burst of 2 Pipelined SRAM with
QDR Architecture
CY7C1306BV25
CY7C1303BV25
Cypress Semiconductor Corporation
Document #: 38-05627 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 3, 2006
Features
Separate independent Read and Write data ports
— Supports concurrent transactions
167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–1.9V)
JTAG Interface
Variable Impedance HSTL
Configurations
CY7C1303BV25 – 1M x 18
CY7C1306BV25 – 512K x 36
Functional Description
The CY7C1303BV25 and CY7C1306BV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR archi-
tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K clock.
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303BV25/
CY7C1306BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter-
faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing perfor-
mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303BV25) or two
36-bit words (CY7C1306BV25) that burst sequentially into or
out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1303BV25 | 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM) |
| CY7C1310BV18 | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1314BV18 | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1314BV18-167BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1314BV18-200BZC | 18-Mbit QDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1306CV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512x36 QDR Burst2 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308BV25-167BZC | 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk |
| CY7C1308DV25-250BZC | 制造商:Cypress Semiconductor 功能描述:256KX36 2.5V DDR SRAM (4-WORD BURST) - Bulk |
| CY7C1308DV25C-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1308DV25C-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 2.5V DDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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