參數(shù)資料
型號： CY7C1306BV25
廠商： Cypress Semiconductor Corp.
英文描述： 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM)
中文描述： 18兆位的2四年防務(wù)審查架構(gòu)（18Mbit，2突發(fā)流水線SRAM的突發(fā)，國防評估報告結(jié)構(gòu)，流水線的SRAM）
文件頁數(shù)： 7/19頁
文件大?。?/td> 821K
代理商： CY7C1306BV25
CY7C1306BV25
CY7C1303BV25
Document #: 38-05627 Rev. *A
Page 7 of 19
Write Descriptions (CY7C1303BV25)
[2, 8]
BWS
0
L
L
L
BWS
1
L
L
H
K
K
-
Comments
L-H
-
L-H
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
remains unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
remains unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into the device.
D
[8:0]
remains unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into the device.
D
[8:0]
remains unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L-H
-
L
H
-
L-H
H
L
L-H
-
H
L
-
L-H
H
H
H
H
L-H
-
-
L-H
Write Descriptions (CY7C1306BV25)
[2, 8]
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
-
Comments
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L
L
L
-
L-H
L
H
H
H
L-H
-
L
H
H
H
-
L-H
H
L
H
H
L-H
-
H
L
H
H
-
L-H
H
H
L
H
L-H
-
H
H
L
H
-
L-H
H
H
H
L
L-H
-
H
H
H
L
-
L-H
H
H
H
H
H
H
H
H
L-H
-
-
L-H
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
, BWS
, in the case of CY7C1303BV25 and also BWS
and BWS
3
in the case of CY7C1306BV25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. 38-05627
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PDF描述
CY7C1303BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 2，QDR結(jié)構(gòu)，流水線SRAM)
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