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參數(shù)資料
| 型號： | CY7C09579V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 32K x 36 FLEx36 Synchronous Dual-Port Static RAM(3.3V 32K x 36 同步雙端口靜態(tài) RAM) |
| 中文描述： | 3.3 32K的× 36 FLEx36同步雙端口靜態(tài)RAM（3.3 32K的× 36同步雙端口靜態(tài)RAM）的 |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 1059K |
| 代理商： | CY7C09579V |
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CY7C09569V
CY7C09579V
Document #: 38-06054 Rev. *B
Page 2 of 30
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3V
synchronous CMOS 16K and 32K x 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid t
CD2
= 5 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available
t
CD1
= 12.5 ns
after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
external R/W LOW duration. The internal write pulse is self-
timed to allow the shortest possible cycle times.
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the
pipelined mode, one cycle is required with CE LOW to
reactivate the outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 144-Pin Thin Quad Plastic Flatpack
(TQFP), 144-Pin Pb-Free Thin Quad Plastic Flatpack (TQFP)
and 172-Ball Ball Grid Array (BGA) packages.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1018CV33-12VC | 128K x 8 Static RAM |
| CY7C1018CV33-15VC | 128K x 8 Static RAM |
| CY7C1018CV33-8VC | 128K x 8 Static RAM |
| CY7C1020CV33-10ZC | 32K x 16 Static RAM |
| CY7C1020-12ZC | 32K x 16 Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C09579V-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09579V-100AXC | 功能描述:靜態(tài)隨機存取存儲器 3.3V 32Kx36 COM SYNC DUAL PORT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09579V-100BBC | 功能描述:靜態(tài)隨機存取存儲器 3.3V 32Kx36 COM SYNC DUAL PORT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09579V-67AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1.125M-Bit 32K x 36 20ns/8ns 144-Pin TQFP |
| CY7C09579V-83AC | 功能描述:IC SRAM 1MB SYNC 144-TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
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