參數(shù)資料
型號(hào): CY7C1018CV33-12VC
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 128K x 8 Static RAM
中文描述: 128K X 8 STANDARD SRAM, 12 ns, PDSO32
封裝: 0.300 INCH, SOJ-32
文件頁(yè)數(shù): 1/7頁(yè)
文件大?。?/td> 132K
代理商: CY7C1018CV33-12VC
128K x 8 Static RAM
CY7C1018CV33
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *C
3901 North First Street
San Jose
CA 95134
Revised September 13, 2002
408-943-2600
Features
Pin- and function-compatible with CY7C1018BV33
High speed
—t
AA
= 8, 10, 12, 15 ns
CMOS for optimum speed/power
Center power/ground pinout
Data retention at 2.0V
Automatic power-down when deselected
Easy memory expansion with CE
and OE options
Available in 300-mil-wide 32-pin SOJ
Functional Description
[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Logic Block Diagram
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Note:
1.
For guidelines on SRAM system designs, please refer to the
System Design Guidelines
Cypress application note, available on the internet at www.cypress.com.
1
A
1
A
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512 x 256 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
A
1
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
SOJ
29
32
31
30
16
17
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
A
13
OE
I/O
7
I/O
6
V
SS
A
16
A
15
A
14
A
12
A
11
A
10
A
9
A
8
I/O
2
I/O
3
WE
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
Selection Guide
7C1018CV33-8
8
95
5
7C1018CV33-10
10
90
5
7C1018CV33-12
12
85
5
7C1018CV33-15
15
80
5
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
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參數(shù)描述
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