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| 型號(hào)： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
FastEdge Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 3 of 11
Absolute Maximum Conditions
Parameter
V
cc
Supply Voltage
V
cc
Operating Voltage
V
BB
Output Reference Voltage
I
BB
Output Reference Current
V
TT
Output Termination Voltage
V
IN
Input Voltage
V
OUT
Output Voltage
LU
I
Latch-up Immunity
T
S
Temperature, Storage
T
A
Temperature, Operating Ambient
T
J
Temperature, Junction
Jc
Dissipation, Junction to Case
Ja
Dissipation, Junction to Ambient
ESD
h
ESD Protection (Human Body Model)
M
SL
Moisture Sensitivity Level
G
ATES
Total Functional Gate Count
UL–94
Flammability Rating
FIT
Failure in Time
Description
Condition
Min.
–0.3
2.5 – 5%
V
CC
–1.525
Max.
3.6
3.3 + 5%
Vcc–1.325
200
VCC–2
V
CC
+0.3
V
CC
+0.3
Unit
VDC
VDC
VDC
uA
VDC
VDC
VDC
mA
°C
°C
°C
°C/W
°C/W
V
N.A.
Ea.
N.A.
PPM
Non-functional
Functional
Relative to V
CC
Relative to V
BB
V
TT
= 0V for V
CC
= 2.5V
Relative to V
CC
Relative to V
CC
Functional
Non-functional
Functional
Functional
Functional
Functional
–0.3
–0.3
300
–65
–40
10
+150
+85
+110
TBD
TBD
2000
TBD
50
V–0
TBD
Assembled Die
@1/8 in
Manufacturing Test
PECL DC Electrical Specifications
Parameter
V
IL
Input Voltage, Low
V
IH
Input Voltage, High
I
IN
Description
Condition
Min.
Max.
Unit
V
V
uA
V
CC
–1.945
V
CC
–1.625
V
CC
–0.880
200
Define VCC and Load Current V
CC
–1.165
V
IN
= V
IL
or V
IN
= V
IH
Input Current
[4]
Clock input pair CLKA, CLKA#,CLKB, CLKB#
(PECL Differential Signals)
V
PP
V
CMR
I
IN
Differential Input Voltage
[5]
Differential Cross Point Voltage
[6]
Input Current
[4]
Differential Operation
Differential Operation
V
IN
= V
IL
or V
IN
= V
IH
0.1
1.2
1.3
V
CC
200
V
V
uA
PECL Outputs Q0-Q19, (Q0-Q19)#(PECL Differential Signals)
V
OH
Output High Voltage
V
OL
Output Low Voltage
V
CC
= 3.3V ±5%V
CC
= 2.5V ±5%
I
OH
= –30 mA
[9]
, 50
Load
I
OL
= –5 ma
[9]
,50
Load
V
CC
–1.145
V
CC
–1.945
V
CC
–1.945
V
CC
–0.895
V
CC
–1.695
V
CC
–1.695
V
V
Clock Input Pair CLKA, CLKA#,CLKB, CLKB# (HSTL Differential Signals)
V
DIF
V
X
I
IN
Input Current
Notes:
4.
Input have internal pullup / pulldown or biasing resistors which affect the input current.
5.
VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
6.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input
swing lies within the VPP (DC) specification.
7.
VDIF (DC) is the amplitude of the differential HSTL input voltage swing required for device functionality.
8.
VX (DC) is the crosspoint of the differential HSTL input signal. Functional operations is obtained when the crosspoint is within the VX (DC) range and the input
swing lies within the VPP (DC) specification.
9.
Differential Input Voltage
[7]
Differential Cross Point Voltage
[8]
0.4
0.68
1.9
0.9
200
V
V
uA
Vin = Vx ± 0.2V
Equivalent to a termination of 50
to VTT.
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