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參數(shù)資料
| 型號： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
FastEdge Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 2 of 11
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below.
Notes:
1.
In the I/O column, the following notation is used: I = Input, O = Output, PD = Pull-down, PU = Pull-up, PC = Pull Center, O = Output, OS = Open Source,
PWR = Power.
in ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND(0V). In PECL mode (positive power supply mode),
VEE is connected to GND(0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
VBB is available for use for single ended bias mode when VCC is +3.3V.
2.
3.
Pin Description
Pin
Name
I/O
Type
Description
4,5
CLKA, CLKA# I,PD
[1]
I,PC
ECL/PECL
Default differential clock input pair
7,8
CLKB, CLKB# I,PD
I,PC
I,PD
O,OS
HSTL
Alternate differential clock input pair
3
52,50,48,46,44,42,39,3
7,35,33,31,29,26,24,22
,20,18,16,13,11
51,49,47,45,43,41,38,3
6,34,32,30,28,25,23,21
,19,17,15,12,10
6
CLK_SEL
Q[0-19]
ECL/PECL
ECL/PECL
CLK – Mux select
True output
Q#[0-19]
O,OS
ECL/PECL
Complement output
VBB
[3]
O
Bias
Reference voltage output for single-ended ECL or PECL
operation
Power supply, negative connection
Power supply, positive connection
Power supply, positive connection
9
2
1,14,27,40
VEE
[2]
VCC
VCCO
-PWR
+PWR
+PWR
Power
Power
Power
Agency Name
JEDEC
Specification
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–A (Skew,Jitter)
JESD 8-6 (HSTL)
1596.3 (Jitter Specs)
94 (Moisture Grading)
883E Method 1012.1
(Thermal Theta JC)
IEEE
UL
Mil–Spec
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2DP3120AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AXIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP314 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:4 Differential Clock/Data Fanout Buffer |
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