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參數(shù)資料
| 型號： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
1:20 Differential Clock Buffer/Driver
FastEdge Series
CY2DP3120
Cypress Semiconductor Corporation
Document #: 38-07514 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 16, 2003
Features
Twenty ECL/PECL differential outputs
Two ECL-/PECL-/HSTL-compatible differential clock
inputs
Hot-swappable/-insertable
50-ps output-to-output skew
500-ps device-to-device skew
Less than 10-ps intrinsic jitter
< 500-ps propagation delay (typical)
Operation from DC to 1.5 GHz
PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
ECL mode supply range: V
EE
= –2.375V to –3.465V with
V
CC
= 0V
Industrial temperature range: –40
°
C to 85
°
C
52-pin 1.4-mm TQFP package
Temperature compensation like 100K ECL
Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device is fully differential and features two reference input
buffers. The CY2DP3120 may function not only as a differ-
ential clock buffer but also as a signal level translator and
fanout distributing a single-ended signal to twenty ECL/PECL
differential loads. An external bias pin, VBB, is provided for an
ECL/PECL/HSTL single-ended or differential. In such an appli-
cation, the VBB pin should be connected to either one of the
CLKA# or CLKB# inputs and bypassed to VCC via a 0.01-
μ
F
capacitor. Traditionally, in ECL, it is used to provide the
reference level to a receiving single ended input that might
have a different self bias point.
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
Pin Configuration
CLKA
CLKA#
VCC
CLKB
CLKB#
VCC
Q0
Q0#
Q19
Q19#
CLK_SEL
VEE
VEE
VEE
VEE
0
1
VEE
VBB
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Q10
Q10#
Q11
Q11#
VCCO
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
V
VCCO
VCC
CLK_SEL
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
Q19#
Q19
Q18#
Q18
V
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
26
25
24
23
22
21
20
19
18
17
16
15
39
38
37
36
35
34
33
32
31
30
29
28
27
CY2DP3120
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY2DP3120AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AXIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP314 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:4 Differential Clock/Data Fanout Buffer |
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