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參數(shù)資料
| 型號(hào)： | CY2PP3115 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 246K |
| 代理商： | CY2PP3115 |
PRELIMINARY
1:15 Differential Fanout Buffer
FastEdge Series
CY2PP3115
Cypress Semiconductor Corporation
Document #: 38-07502 Rev.*A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 18, 2003
Features
Fifteen ECL/PECL differential outputs grouped in four
banks
Two ECL/PECLdifferential inputs
Hot-swappable/-insertable
50-ps output-to-output skew
< 200-ps device-to-device skew
Less than 2-pS intrinsic jitter
< 500-ps propagation delay (typical)
Operation up to 1.5 GHz
PECL mode supply range: V
CC
= 2.375V to 3.465V with
V
EE
= 0V
ECL mode supply range: V
EE
= –2.375V to –3.465V with
V
CC
= 0V
Industrial temperature range: –40
°
C to 85
°
C
52-pin 1.4mm TQFP package
Temperature compensation like 100K ECL
Description
The CY2PP3115 is a low-skew, low propagation delay 1-to-15
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low-signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths which are
multiplexed internally. This mux is controlled by the CLK_SEL
pin. The CY2PP3115 may function not only as a differential
clock buffer but also as a signal level translator and fanout on
ECL/PECL single-ended signal to 15 ECL/PECL differential
loads. An external bias pin, VBB, is provided for this purpose.
In such an application, the VBB pin should be connected to
either one of the CLKA# or CLKB# inputs and bypassed to V
CC
via a 0.01-
μ
F capacitor.
Since the CY2PP3115 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3115 delivers consistent, guaranteed
performance over differing platforms.
Block Diagram
Pin Configuration
CY2PP3115
1
2
3
4
5
6
7
8
9
10
11
12
13
1
1
1
1
1
1
2
2
2
2
2
2
2
5
5
5
4
4
4
4
4
4
4
4
4
4
39
38
37
36
35
34
33
32
31
30
29
28
27
VCC
QC0
QC0#
QC1
QC1#
QC2
QC2#
QC3
QC3#
VCC
NC
NC
VCC
V
Q
Q
Q
Q
V
Q
Q
Q
Q
Q
Q
V
VCC
MR
FSELA
FSELB
CLK0
CLK0#
CLK_SEL
CLK1
CLK1#
VBB
FSELC
FSELD
VEE
V
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
0
1
1
0
0
1
QAO
QA1
QBO
QB1
QB2
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QD3
QD4
QD5
VBB
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VCC
VCC
0
1
/1
/2
FSELA
CLK0
CLK0#
CLK1
FSELB
FSELC
MR
FSELD
CLK_SEL
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| CY2PP318 | Clocks and Buffers |
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| CY2PP3220 | Clocks and Buffers |
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| CZT2222 | NPN SILICON TRANSISTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2PP3115AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:15 Differential Fanout Buffer |
| CY2PP3115AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:15 Differential Fanout Buffer |
| CY2PP3115AXI | 制造商:Cypress Semiconductor 功能描述:2.5V OR 3.3V, 1.5GHZ 1:15 LVPECL BUFFER/DIVIDER - Bulk |
| CY2PP318 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY2PP318JI | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5V or 3.3V 1.5GHz IND RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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