參數(shù)資料
型號(hào)： CY28441ZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Clock Generator for Intel Alviso Chipset
中文描述： 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 261K
代理商： CY28441ZXC
CY28441
Document #: 38-07679 Rev. **
Page 8 of 20
Crystal Recommendations
The CY28441 requires a Parallel Resonance Crystal.
Substi-
tuting a series resonance crystal will cause the CY28441 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading. See
Table 5
.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1
shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[0:1]# Description
The CLKREQ#[A:B] signals are active LOW input used for
clean enabling and disabling selected SRC outputs. The
outputs controlled by CLKREQ#[A:B] are determined by the
settings in register byte 8. The CLKREQ# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or de-assertion. (The assertion and
deassertion of this signal is absolutely asynchronous.)
Table 5. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut
Loading
Load Cap
Drive
(max.)
0.1 mW
Shunt Cap
(max.)
5 pF
Motional
(max.)
0.016 pF
Tolerance
(max.)
35 ppm
Stability
(max.)
30 ppm
Aging
(max.)
5 ppm
AT
Parallel
20 pF
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce
= 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
相關(guān)PDF資料
PDF描述
CY28441ZXCT Clock Generator for Intel Alviso Chipset
CY29653 3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8輸出零延遲緩沖器)
CY29774 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14輸出零延遲緩沖器)
CY29942AC 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
CY29942AI 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28441ZXCT 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
CY28442 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset
CY28442-2 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset
CY28442-2_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset
CY28442ZXC 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
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