參數(shù)資料
型號(hào)： CY28441ZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： XO, clock
英文描述： Clock Generator for Intel Alviso Chipset
中文描述： 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 261K
代理商： CY28441ZXC
CY28441
Document #: 38-07679 Rev. **
Page 3 of 20
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode. See
Table 1
.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operations from the controller.
For Block Write/Read operation, the bytes must be accessed
in sequential order from lowest to highest byte (most signif-
icant bit first) with the ability to stop after any complete byte
has been transferred. For Byte Write and Byte Read opera-
tions, the system controller can access individually indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 2
.
The Block Write and Block Read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
50
49
XIN
XOUT
I
14.318-MHz crystal input
.
O, SE
14.318-MHz crystal output
.
Pin Description
Pin No.
Name
Type
Description
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
1
0
0
0
0
1
1
1
FS_B
0
0
1
1
0
0
1
1
FS_A
1
1
1
0
0
0
0
1
CPU
100 MHz
133 MHz
SRC
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
REF0
DOT96
96 MHz
96 MHz
USB
48 MHz
48 MHz
14.318 MHz
14.318 MHz
RESERVED
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block Read or Block Write operation, 1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
8:2
9
10
18:11
19
Bit
1
8:2
9
10
18:11
19
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28441ZXCT 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
CY28442 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset
CY28442-2 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset
CY28442-2_05 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset
CY28442ZXC 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類(lèi)型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
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