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參數(shù)資料
| 型號(hào)： | CY28441ZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Generator for Intel Alviso Chipset |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 261K |
| 代理商： | CY28441ZXC |
CY28441
Document #: 38-07679 Rev. **
Page 10 of 20
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300
μ
s of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other.
Figure 5
is an example showing the relationship of
clocks coming up.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z.
Figure 5. Power-down Deassertion Timing Waveform
DOT96C
PD
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8nS
PCI, 33MHz
REF
Tdrive_PWRDN#
<300
S, >200mV
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28441ZXCT | Clock Generator for Intel Alviso Chipset |
| CY29653 | 3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8輸出零延遲緩沖器) |
| CY29774 | 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14輸出零延遲緩沖器) |
| CY29942AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AI | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28441ZXCT | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| CY28442 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442ZXC | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
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