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參數(shù)資料
| 型號(hào)： | CY29653 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8輸出零延遲緩沖器) |
| 中文描述： | 3.3V的125 - MHz的8路輸出零延遲緩沖器（3.3伏，125MHz的，8輸出零延遲緩沖器） |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | CY29653 |
3.3V 125-MHz 8-Output Zero Delay Buffer
CY29653
Cypress Semiconductor Corporation
Document #: 38-07477 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 13, 2004
Features
Output frequency range: 25 MHz to 125 MHz
Input frequency range (
÷
4): 35 MHz to 125 MHz
Input frequency range (
÷
8): 25 MHz to 62.5 MHz
30 ps typical peak cycle-to-cycle jitter
30 ps typical out-to-output skew
3.3V operation
Eight Clock outputs: Drive up to 16 clock lines
One feedback output
LVPECL reference clock input
Phase-locked loop (PLL) bypass mode
Spread Aware
Output enable/disable
Pin-compatible with MPC9653 and MPC953
Industrial temperature range: –40°C to +85°C
32-pin 1.0-mm TQFP package
Description
The CY29653 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29653 features an LVPECL
reference clock input and provides eight outputs plus one
feedback output. VCO output divides by four or eight per
VCO_SEL setting (see the
Function Table).
Each
LVCMOS-compatible output can drive 50
series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:16.
The PLL is ensured stable given that the VCO is configured to
run between 140 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see the
Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:9 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation both
PLL_EN and BYPASS# are set HIGH.
Block Diagram
Pin Configuration
Phase
Detector
LPF
VCO
200-500MHz
÷
4
÷
2
PECL_CLK
PECL_CLK#
FB_IN
VCO_SEL
BYPASS#
MR/OE#
PLL_EN
FB_OUT
Q(0:6)
Q7
CY29653
V
B
P
V
F
V
Q
V
P
M
V
Q
V
Q
V
Q
Q1
VDDQ
Q2
VSS
Q3
VDDQ
Q4
VSS
AVDD
FB_IN
NC
NC
NC
NC
AVSS
PECL_CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29774 | 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14輸出零延遲緩沖器) |
| CY29942AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AI | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AIT | CONN SMART CARD 8PIN W/DETECT |
| CY29942ACT | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29653AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AXC | 功能描述:鎖相環(huán) - PLL 2.5 or 3.3V 125MHz COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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