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參數(shù)資料
| 型號(hào)： | CY29653 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8輸出零延遲緩沖器) |
| 中文描述： | 3.3V的125 - MHz的8路輸出零延遲緩沖器（3.3伏，125MHz的，8輸出零延遲緩沖器） |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 212K |
| 代理商： | CY29653 |
CY29653
Document #: 38-07477 Rev. *C
Page 2 of 7
Pin Description
[1]
Pin
Name
I/O
Type
Description
8
9
12, 14, 16,
18, 20, 22,
24, 26
28
2
PECL_CLK
PECL_CLK#
Q(7:0)
I, PU
I, PU
O
LVPECL
LVPECL
LVCMOS
LVPECL reference clock input
LVPECL reference clock input
. Pull-up to VDD/2.
Clock output
FB_OUT
FB_IN
O
I, PU
LVCMOS
LVCMOS
Feedback clock output
. Connect to FB_IN for normal operation.
Feedback clock input
. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Frequency Table.
Output enable/disable input
. See Function Table.
PLL enable/disable input
. See Function Table.
PLL and output divider bypass select input
. See Function Table.
VCO divider select input
. See Function Table.
3.3V Power supply for output clocks
[2]
3.3V Power supply for PLL
[2]
3.3V Power supply for core and inputs
[2]
Analog Ground
Common Ground
10
30
31
32
11, 15, 19, 23 VDDQ
1
27
7
13, 17, 21,
25, 29
3, 4, 5, 6
MR/OE#
PLL_EN
BYPASS#
VCO_SEL
I, PD
I, PU
I, PU
I, PU
Supply
Supply
Supply
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
Ground
Ground
AVDD
VDD
AVSS
VSS
NC
No connection
Frequency Table
Feedback Output Divider
÷
4
÷
8
VCO
Input Frequency Range
35 MHz to 125 MHz
25 MHz to 62.5 MHz
Input Clock * 4
Input Clock * 8
Function Table
Control
VCO_SEL
PLL_EN
Default
1
1
0
1
VCO
÷
1
Bypass mode, PLL disabled. The input
clock connects to the output dividers
Bypass mode with PLL and output
dividers bypassed. The input clock
connects to the outputs.
Outputs enabled
VCO
÷
2
PLL enabled. The VCO output connects to the
output dividers
Selects the output dividers
BYPASS#
1
MR/OE#
0
Outputs disabled (three-state), VCO running at
its minimum frequency
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-
μ
F bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29774 | 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14輸出零延遲緩沖器) |
| CY29942AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AI | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AIT | CONN SMART CARD 8PIN W/DETECT |
| CY29942ACT | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29653AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AXC | 功能描述:鎖相環(huán) - PLL 2.5 or 3.3V 125MHz COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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