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參數(shù)資料
| 型號： | CY29653 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 125-MHz 8-Output Zero Delay Buffer(3.3V, 125MHz, 8輸出零延遲緩沖器) |
| 中文描述： | 3.3V的125 - MHz的8路輸出零延遲緩沖器（3.3伏，125MHz的，8輸出零延遲緩沖器） |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CY29653 |
CY29653
Document #: 38-07477 Rev. *C
Page 4 of 7
Note:
7. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input swing lies
within the V
PP
(AC) specification. Violation of V
CMR
or V
PP
impacts static phase offset t(
φ
).
V
CMR
f
MAX
Common Mode Range
[7]
Maximum Output Frequency
LVPECL
÷
4 Output
÷
8 Output
1.2
35
25
45
0.1
–200
–
–
–
–
–
–
VDD – 0.9
125
62.5
55
1.0
200
V
MHz
DC
t
r
, t
f
t
(
φ
)
Output Duty Cycle
Output Rise/Fall times
Propagation Delay (static phase
offset)
Propagation Delay (PLL and
divider bypass)
Output-to-Output Skew
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
(–3 dB)
%
ns
ps
0.55V to 2.4V
PCLK to FB_IN
t
PD
PCLK to Q0 – Q7
BYPASS# = 0
3.6
4.8
6.0
ns
t
sk(O)
t
PLZ, HZ
t
PZL, ZH
BW
–
–
–
–
–
–
–
–
–
30
–
–
150
6
6
–
–
100
100
150
1
ps
ns
ns
MHz
÷
4 Feedback
÷
8 Feedback
1.8 – 2.1
1.4 – 1.6
30
45
–
–
t
JIT(CC)
t
JIT(PER)
t
JIT(
φ
)
t
LOCK
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
Maximum PLL Lock Time
ps
ps
ps
ms
AC Parameters
(V
DD
= 3.3V ± 5%, T
A
= operating temperature range) (continued)
[3]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
R
T
= 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 1. AC Test Reference
t(
φ)
PECL_CLK
PECL_CLK
V
PP
FB_IN
V
CMR
VDD
GND
VDD/2
Figure 2. Propagation Delay t(
φ
), Static Phase Offset
tPD
PECL_CLK
PECL_CLK
V
PP
Qn
V
CMR
VDD
GND
VDD/2
Figure 3. Propagation Delay t
PD
, PLL Bypass
相關PDF資料 |
PDF描述 |
|---|---|
| CY29774 | 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer(2.5V/3.3V, 125MHz, 14輸出零延遲緩沖器) |
| CY29942AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AI | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29942AIT | CONN SMART CARD 8PIN W/DETECT |
| CY29942ACT | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY29653AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 125-MHz 8-Output Zero Delay Buffer |
| CY29653AXC | 功能描述:鎖相環(huán) - PLL 2.5 or 3.3V 125MHz COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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