參數(shù)資料
型號: CY28441ZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Clock Generator for Intel Alviso Chipset
中文描述: 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁數(shù): 5/20頁
文件大?。?/td> 261K
代理商: CY28441ZXC
CY28441
Document #: 38-07679 Rev. **
Page 5 of 20
2
1
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1
1
SRC[T/C]1
0
1
SRC[T/C]0
Byte 0:Control Register 0
(continued)
Bit
@Pup
Name
Description
Byte 1: Control Register 1
Bit
7
@Pup
1
Name
PCIF0
Description
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
Reserved
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
6
1
DOT_96T/C
5
1
USB_48
4
1
REF
3
2
0
1
Reserved
CPU[T/C]1
1
1
CPU[T/C]0
0
0
CPUT/C
SRCT/C
PCIF
PCI
Byte 2: Control Register 2
Bit
7
@Pup
1
Name
PCI5
Description
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI Output Drive strength
0 = Low drive 1 = High drive
Reserved, Set = 1
Reserved, Set = 1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI4
5
1
PCI3
4
1
PCI2
3
1
PCI
2
1
0
1
1
1
Reserved
Reserved
PCIF1
Byte 3: Control Register 3
Bit
7
@Pup
0
Name
SRC7
Description
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
0
0
RESERVED
SRC5
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PDF描述
CY28441ZXCT Clock Generator for Intel Alviso Chipset
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