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參數(shù)資料
| 型號(hào)： | CY28347 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | HDC-HA-48-SVL1/29 RoHS Compliant: Yes |
| 中文描述： | 通用單芯片時(shí)鐘為威盛P4M266/KM266的DDR系統(tǒng)解決方案 |
| 文件頁(yè)數(shù)： | 7/22頁(yè) |
| 文件大小： | 188K |
| 代理商： | CY28347 |
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CY28347
Document #: 38-07352 Rev. *C
Page 7 of 22
Table 8. Dial-A-Ratio
AGP(0:2)
DARAG (1:0)
00
01
10
11
CU/AGP Ratio
Frequency Selection Default
2/1
2.5/1
3/1
Byte 5: DDR Clock Register
Bit
7
6
@Pup
0
1
Pin#
45
46
Name
Description
BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V.
FBOUT
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C5
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C4
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C3
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C2
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C1
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
DDRT/C0
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
5
1
29,30
4
1
31,32
3
1
35,36
2
1
37,38
1
1
41,42
0
1
43,44
Byte 6: Reserve Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
0
0
0
0
0
0
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Byte 7: Dial-a-Frequency Control Register N
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Description
Reserved
N6, MSB
N5
N4
N3
N2
N1
N0, LSB
Reserved for device function test.
These bits are for programming the PLL
’
s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28347ZC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28349B | FTG for Intel Pentium 4 CPU and Chipsets |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28347OC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28347ZCT | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel |
| CY28349 | 制造商:SPECTRALINEAR 制造商全稱(chēng):SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
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