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參數(shù)資料
| 型號： | CY28347 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | HDC-HA-48-SVL1/29 RoHS Compliant: Yes |
| 中文描述： | 通用單芯片時鐘為威盛P4M266/KM266的DDR系統(tǒng)解決方案 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 188K |
| 代理商： | CY28347 |
CY28347
Document #: 38-07352 Rev. *C
Page 16 of 22
CPU_STP# Assertion (K7 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by two rising CPUC clock edges.
The final state of the stopped CPU signal is CPUOD_T = LOW
and CPUOD_C = LOW.
CPU_STP# Deassertion (K7 Mode)
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUOD_T
CPUOD_C
Figure 9. CPU_STP# Assertion Waveform (K7 Mode)
CPU_STP#
CPUCS_T
CPUCS_C
CPUOD_T
CPUOD_C
Figure 10. CPU_STP# Deassertion Waveform (K7 Mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28347ZC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28349B | FTG for Intel Pentium 4 CPU and Chipsets |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28347OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28347ZCT | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel |
| CY28349 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
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