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參數(shù)資料
| 型號： | CY28347 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | HDC-HA-48-SVL1/29 RoHS Compliant: Yes |
| 中文描述： | 通用單芯片時鐘為威盛P4M266/KM266的DDR系統(tǒng)解決方案 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 188K |
| 代理商： | CY28347 |
CY28347
Document #: 38-07352 Rev. *C
Page 14 of 22
CPUT
MULTSEL
T
PCB
T
PCB
CPUC
33
33
49.9
49.9
Measurement Point
2 pF
475
IREF
Measurement Point
2 pF
Figure 5. P4 0.7V Configuration
Table 10. Group Timing Relationships and Tolerances
Offset (ps)
750
500
Tolerance (ps)
500
500
Conditions
CPUCS Leads
AGP Leads
t
CSAGP
t
AP
CPUCS to AGP
AGP to PCI
Table 11. Signal Loading
Clock Name
Max. Load (in pF)
20
30
10
See
Figure 1
See
Figure 4
and
Figure 5
See
Figure 2
See
Figure 3
REF (0:1), 48MHz (USB), 24_48MHz
AGP(0:2), PCI_F(0:5)SDRAM (0:11)
FBOUT
DDRT/C
CPUT/C
CPUOD_T/C
CPUCS_T/C
0 ns
10 ns
20 ns
30 ns
AGP CLOCK 66.6 MHz
PCI CLOCK 33.3 MHz
CPU CLOCK 66.6 MHz
CPU CLOCK 100 MHz
CPU CLOCK 133.3 MHz
t
AP
t
CSAGP
Figure 6. Clock Timing Relationships
相關PDF資料 |
PDF描述 |
|---|---|
| CY28347ZC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28349B | FTG for Intel Pentium 4 CPU and Chipsets |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28347OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28347ZCT | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel |
| CY28349 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
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