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參數(shù)資料
| 型號(hào)： | CY28347 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | HDC-HA-48-SVL1/29 RoHS Compliant: Yes |
| 中文描述： | 通用單芯片時(shí)鐘為威盛P4M266/KM266的DDR系統(tǒng)解決方案 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 188K |
| 代理商： | CY28347 |
CY28347
Document #: 38-07352 Rev. *C
Page 19 of 22
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a LOW level in an orderly fashion prior to removing power
from the CPU. When PD# is sampled LOW by two consecutive
rising edges of the CPUCS_C clock, then all affected clocks
are stopped in a LOW state after the next HIGH to LOW
transition or remains LOW. When in power-down (and before
power is removed), all outputs are synchronously stopped in a
LOW state (see
Figure 15
below), all PLLs are shut off, and
the crystal oscillator is disabled. When the device is shutdown,
the I2C function is also disabled.
Power Down Deassertion (K7 Mode)
When deasserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
order to guarantee a glitch-free operation, no partial clock
pulses.
PCI 33MHz
PWRDWN#
REF 14.318MHz
USB 48MHz
DDRT 133MHz
DDRC 133MHz
AGP 66MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
CPUOD_T 133MHz
CPUCS_T 133MHz
Figure 15. Power-down Assertion Timing Waveform (in K7 Mode)
PCI 33MHz
PWRDWN#
AGP 66MHz
REF 14.318MHz
USB 48MHz
<1.5 msec
DDRT 133MHz
DDRC 133MHz
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
Figure 16. Power-down Deassertion Timing Waveform (in K7 Mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28347ZC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28349B | FTG for Intel Pentium 4 CPU and Chipsets |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28347OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347ZC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28347ZCT | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Tape and Reel |
| CY28349 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
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