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參數(shù)資料
| 型號(hào)： | CY28341ZC |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁(yè)數(shù)： | 9/21頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | CY28341ZC |
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CY28341
Document #: 38-07367 Rev. *A
Page 9 of 21
System Self-recovery Clock Management
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang-up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through Byte 4 or through Bytes 13 and 14,
it must have previously sent a command to Byte 12, for
selecting which time out stamp the Watchdog must perform,
otherwise the System Self Recovery feature will not be appli-
cable. Consequently, this device will change frequency and
then the Watchdog timer starts timing. Meanwhile, the system
BIOS is running its operation with the new frequency. If this
device receives a new SMBus command to clear the bits origi-
nally programmed in Byte 12,Bits (3:0) (reprogram to 0000),
before the Watchdog times out, then this device will keep
operating in its normal condition with the new selected
frequency. If the Watchdog times out the first time before the
new SMBus reprograms Byte12,Bits (3:0) to (0000), then this
device will send a low system reset pulse, on SRESET# (see
Byte12,Bit7), and changes WD alarm (Byte12,Bit4) status to
“
1
”
then restarts the Watchdog timer again. If the Watchdog
times out a second time, then this device will send another low
pulse on SRESET#, will relatch original hardware strapping
frequency (or second to last software selected frequency, see
Byte12,Bit6) selection, set WD alarm bit (Byte12,Bit4) to
“
1,
”
then start WD timer again. The above-described sequence will
keep repeating until the BIOS clears the SMBus
Byte12,Bits(3:0). Once the BIOS sets Byte12,Bits(3:0) = 0000,
then the Watchdog timer is turned off and the WD alarm bit
(Byte12,Bit4) is reset to
”
0.
”
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire
control interface. All clocks are stopped in the LOW state. All
clocks maintain a valid HIGH period on transitions from
running to stop and on transitions from stopped to running
when the chip was not powered down. On power-up, the
VCOs will stabilize to the correct pulse widths within about 0.5
mS.
Table 9. Spread Spectrum Table
Mode
0
0
0
0
1
1
1
1
SST1
0
0
1
1
0
0
1
1
SST0
0
1
0
1
0
1
0
1
% Spread
–
1.5%
–
1.0%
–
0.7%
–
0.5%
±0.75%
±0.5%
±0.35%
±0.25%
Swing Select Functions Through Hardware
MULT-
SEL
0
Board Target
Trace/Term Z
50 Ohm
Reference R,
IREF = VDD/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Output
Current VOH@Z
IOH = 4 *
Iref
IOH = 6 *
Iref
1.0V@50
1
50 Ohm
0.7V@50
S y s t e m r u n n in g w it h
o r ig in a lly s e le c t e d
f r e q u e n c y v ia
h a r d w a r e s t r a p p in g .
R e c e iv e F r e q u e n c y
C h a n g e R e q u e s t v ia
S M B u s B y t e 4 o r V ia D ia l-
a - f r e q u e n c y
S t a r t in t e r n a l w a t c h d o g t im e r .
W a t c h D o g t im e o u t
T u r n o f f w a t c h d o g t im e r .
K e e p n e w f r e q u e n c y s e t t in g . S e t W D a la r m
b it ( b y t e 1 2 , b it 4 ) t o
’’
0
’
1 ) S e n d a n o t h e r 3 m S lo w p u ls e o n S R E S E T
2 ) R e la t c h o r ig in a l h a r d w a r e s t r a p p in g s e le c t io n
f o r r e t u r n t o o r ig in a l f r e q u e n c y s e t t in g s .
3 ) S e t W D A la r m b it ( b y t e 1 2 , B it 4 ) t o " 1 "
4 ) S t a r t W D t im e r
F r e q u e n c y w ill c h a n g e b u t S y s t e m S e lf
R e c o v e r y n o t a p p lic a b le ( n o t im e s t a m p
s e le c t e d a n d b y t e 1 2 , b it ( 3 : 0 ) is s t ill =
" 0 0 0 0 "
N o
N o
Y e s
N o
N o
Y e s
S M B u s b y t e 1 2 t im e
o u t s t a m p d is a b le d
I s S M B u s B y t e 9 , t im e o u t
s t a m p e n a b le d - ( b y t e 1 2 , b it
( 3 : 0 ) 0 0 0 0 )
C h a n g e t o a n e w
f r e q u e n c y
Y e s
1 ) S e n d S R E S E T
p u ls e
2 ) S e t W D b it
( b y t e 1 2 , b it 4 ) t o
’
1
’
3 ) S t a r t W D t im e r
Y e s
W a t c h D o g t im e o u t
N o
Y e s
S M B u s b y t e 9 t im e o u t
s t a m p d is a b le d , B y t e
1 2 , b it ( 3 : 0 ) = ( 0 0 0 0 )
Y e s
N o
Figure 1.
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參數(shù)描述 |
|---|---|
| CY28341ZC-2 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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| CY28341ZC-3 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZC-3T | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZCT | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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