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參數(shù)資料
| 型號： | CY28341ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 189K |
| 代理商： | CY28341ZC |
CY28341
Document #: 38-07367 Rev. *A
Page 13 of 21
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode)
When PD# is sampled LOW by two consecutive rising edges
of CPU# clock then all clock outputs except CPU clocks must
be held LOW on their next HIGH to LOW transition. CPU
clocks must be held with the CPU clock pin driven HIGH with
a value of 2 x Iref, and CPU# undriven. Note that
Figure 4
shows CPU = 133 MHz, this diagram and description is appli-
cable for all valid CPU frequencies 66, 100, 133, 200MHz.Due
to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
PCI 33M Hz
PW RD W N #
CPUT 133M Hz
CPUT# 133M Hz
REF 14.318M Hz
USB 48M Hz
SD RAM 133M Hz
D DRT 133M Hz
DDR C 133M Hz
AG P 66M Hz
Figure 2. Power-down Assertion Timing Waveform (in P4 Mode)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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