參數(shù)資料
型號(hào)： CY28341ZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 14 MM, TSSOP2-56
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 189K
代理商： CY28341ZC
CY28341
Document #: 38-07367 Rev. *A
Page 8 of 21
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via
Byte7 and Byte9. P is a PLL constant that depends on the
frequency selection prior to accessing the Dial-a-Frequency
feature.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is enabled/disabled via SMBus register
Byte 1, Bit 7.
Byte 7: Dial-a-Frequency Control Register N
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Pin#
Name
Description
Reserved
N6, MSB
N5
N4
N3
N2
N3
N0, LSB
Reserved for device function test.
These bits are for programming the PLL
’
s internal N register. This access
allows the user to modify the CPU frequency at very high resolution
(accuracy). All other synchronous clocks (clocks that are generated from
the same PLL, such as PCI) remain at their existing ratios relative to the
CPU clock.
Byte 8: Silicon Signature Register (All bits are Read-only)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Pin#
Name
Description
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vender_ID3
Vender_ID2
Vender_ID1
Vender_ID0
Revision ID bit [3]
Revision ID bit [2]
Revision ID bit [1]
Revision ID bit [0]
Cypress Vender ID bit [3].
Cypress Vender ID bit [2].
Cypress Vender ID bit [1].
Cypress Vender ID bit [0].
Byte9: Dial-A-Frequency Control Register R
Bit @Pup
7
6
5
4
3
2
1
0
Pin#
Name
Description
0
0
0
0
0
0
0
0
Reserved
These bits are for programming the PLL
’
s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
R5, MSB
R4
R3
R2
R1
R0
DAF_ENB This Edge-trigger bit enables the Dial-a-Frequency N and R bits. It is the transition of this bit
from
“
0
”
to
“
1
”
that latches the N(6:0) and R(5:0) data into the internal N and R registers. The
user must only program a one time
“
1
”
into this bit for every new N and R values
Table 8.
FS(4:0)
P
XXXXX
96016000
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28341ZC-2 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
CY28341ZC-2T 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
CY28341ZC-3 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems
CY28341ZC-3T 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems
CY28341ZCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
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