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參數(shù)資料
| 型號： | CY28341ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 189K |
| 代理商： | CY28341ZC |
CY28341
Document #: 38-07367 Rev. *A
Page 16 of 21
Power-down Deassertion (K7 Mode)
When de-asserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
order to guarantee a glitch-free operation, no partial clock
pulses.
Note:
31. This time diagram shows that VTT_PWRGD# transits to a logic LOW in the first time at power-up. After the first HIGH to LOW transition of VTT_PWRGD#,
device is not affected, VTT_PWRGD# is ignored.
PCI 33MHz
PW RDW N#
CPU 133MHz
CPU# 133MHz
AGP 66MHz
REF 14.318MHz
USB 48MHz
<1.5 msec
SDRAM 133MHz
DDRT 133MHz
DDRC 133MHz
Figure 5. Power-down Deassertion Timing Waveform (in K7 mode)
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_GD#
Sample Sels
Off
Off
On
On
State 1
(Note A)
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)
[31]
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|---|---|
| CY28341ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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