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參數(shù)資料
| 型號： | CY28341ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY28341ZC |
CY28341
Document #: 38-07367 Rev. *A
Page 6 of 21
Byte 2: PCI Clock Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
Pin#
Name
PCI_DRV
PCI_F
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Description
PCI clock output drive strength 0 = Normal, 1 = increase the drive strength 20%.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
10
18
17
15
14
12
11
Byte 3: AGP/Peripheral Clocks Register
Bit
7
@Pup
0
Pin#
21
Name
24_48M
Description
“
0
”
= pin21 output is 24MHz. Writing a
“
1
”
into this register asynchronously changes the
frequency at pin21 to 48 MHz.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Programming these bits allow shifting skew of the AGP(0:2) signals relative to their
default value. See
Table 5
.
6
5
4
3
2
1
0
1
1
0
0
1
1
1
20
21
48MHz
24_48M
DASAG1
DASAG0
AGP2
AGP1
AGP0
6,7,8
6,7,8
8
7
6
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
Table 5. Dial-a-Skew
AGP(0:2)
DASAG (1:0)
00
01
10
11
AGP(0:2) Skew Shift
Default
–
280 ps
+280 ps
+480 ps
Byte 4: Peripheral Clocks Register
Bit @Pup Pin#
7
1
Name
48M
Description
20
1 = normal strength, 0 = high strength
1 = normal strength, 0 = high strength
1 = normal strength, 0 = high strength
1 = normal strength, 0 = high strength
DARAG1 Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks
relative to the CPU clocks. See
Table 6
.
DARAG0
REF0
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
REF1
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. (K7 Mode only.)
REF0
1 = normal strength, 0 = high strength
REF1
1 = normal strength, 0 = high strength (K7 Mode only.)
Table 6. Dial-A-Ratio
AGP(0:2)
6
1
21
24_48M
5
4
3
2
1
0
0
0
1
1
1
1
6,7,8
6,7,8
1
56
1
56
DARAG (1:0)
00
01
10
11
CU/AGP Ratio
Frequency Selection Default
2/1
2.5/1
3/1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341ZC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341ZC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZC-3T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
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