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參數(shù)資料
| 型號(hào)： | CY28341-2 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
| 中文描述： | 通用時(shí)鐘芯片的威盛P4M/KT/KM400的DDR系統(tǒng) |
| 文件頁(yè)數(shù)： | 16/19頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | CY28341-2 |
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CY28341-2
Document #: 38-07471 Rev. *B
Page 16 of 19
T
R
/T
F
CPUT/C Rise and Fall Times
Rise/Fall Matching
Rise/Fall Time Variation
CPUCS_T/C to CPUT/C Clock Skew
CPUT/C Cycle to Cycle Jitter
Crossing Point Voltage at 0.7V Swing
P4 Mode CPU at 1.0V
T
DC
CPUT/C Duty Cycle
T
PERIOD
CPUT/C Period
Differential
T
R
/T
F
T
SKEW
CPUCS_T/C to CPUT/C Clock Skew
T
CCJ
CPUT/C Cycle to Cycle Jitter
V
CROSS
Crossing Point Voltage at 1V Swing
SE-DeltaSlew Absolute Single-ended Rise/Fall
Waveform Symmetry
K7 Mode
T
DC
CPUOD_T/C Duty Cycle
T
PERIOD
CPUOD_T/C Period
T
LOW
CPUOD_T/C Low Time
T
F
CPUOD_T/C Fall Time
T
SKEW
CPUCS_T/C to CPUT/C Clock Skew
T
CCJ
CPUOD_T/C Cycle-to-Cycle Jitter
V
D
Differential Voltage AC
V
X
Differential Crossover Voltage
CHIPSET CLOCK
T
DC
CPUCS_T/C Duty Cycle
T
PERIOD
CPUCS_T/C Period
T
R
/ T
F
CPUCS_T/C Rise and Fall Times
V
D
Differential Voltage AC
V
X
Differential Crossover Voltage
175
700
20%
125
200
+150
430
175
700
20%
125
150
+150
430
175
700
20%
125
200
+200
430
ps 24
24,26
T
R
/T
F
T
SKEW
T
CCJ
V
CROSS
ps 8,24,16
ps 8,18,15,16
ps 8,18,15,16
mV 16
0
0
0
–150
280
–150
280
–200
280
45
9.85
175
55
10.2
467
45
7.35
175
55
7.65
467
45
4.85
175
55
5.1
467
% 8,9,15
nS 8,9,15
ps 7,14,27
CPUT/C Rise and Fall times
0
200
+150
760
325
0
150
+150
760
325
0
200
+200
760
325
0
ps 8,14,11
mV 27
ps 26
8,14,11
–150
510
–150
510
–200
510
45
9.98
2.8
0.4
0
–150
.4
500
55
10.5
45
7.5
1.67
0.4
0
–150
.4
500
55
8.0
45
5
2.8
0.4
0
–200
.4
500
55
5.5
% 8,9
ns 8,9
ns 8,9
ns 8,13
0
8,14,11
ps 8,9
V
23
mV 23
1.6
200
+150
Vp+.6V
1100
1.6
150
+150
Vp+.6V
1100
1.6
200
+200
Vp+.6V
1100
45
10.0
0.4
.4
0.5*V
D
D
I–0.2
55
10.5
1.6
Vp+.6V
0.5*V
DD
I
+0.2
45
15
0.4
.4
55
15.5
1.6
Vp+.6V
0.5*V
D
D
I+0.2
45
10.0
0.4
.4
0.5*V
D
D
I–0.2
55
10.5
1.6
Vp+.6V
0.5*V
D
D
I+0.2
% 7,8,9
ns 7,8,9
ns 7,8,13
V
24
V
11
0.5*V
D
D
I–0.2
AGP
T
DC
T
PERIOD
T
HIGH
T
LOW
T
R
/ T
F
Notes:
17. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
18. This measurement is applicable with Spread ON or spread OFF.
19. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
20. Time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till frequency output is stable and operating within specs.
21. The typical value of VX is expected to be 0.5*V
(or 0.5*V
for CPUCS signals) and will track the variations in the DC level of the same.
22. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its comple-
mentary DDRC (and CPUCS_C) one.
23. Measured at VX between the rising edge and the following falling edge of the signal.
24. Measured from V
= 0.175V to V
= 0.525V.
25. Measurement taken from differential waveform, from –0.35V to +0.35V.
26. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is
designed for waveform symmetry.
27. Measured in absolute voltage, i.e., single-ended measurement.
AGP(0:2) Duty Cycle
AGP(0:2) Period
AGP(0:2) High Time
AGP(0:2) Low Time
AGP(0:2) Rise and Fall Times
45
15
5.25
5.05
0.4
55
16
45
15
5.25
5.05
0.4
55
16
45
15
5.25
5.05
0.4
55
16
% 7,8,9
ns 7,8,9
ns 8,21
ns 8,10
ns 8,13
1.6
1.6
1.6
AC Parameters
(continued)
Parameter
Description
100 MHz
Min.
133 MHz
Min.
200 MHz
Min.
Unit
Notes
Max.
Max
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341-2_05 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341-3 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk |
| CY28341OC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28341OC-2T | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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