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參數(shù)資料
| 型號： | CY28341-2 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
| 中文描述： | 通用時鐘芯片的威盛P4M/KT/KM400的DDR系統(tǒng) |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 174K |
| 代理商： | CY28341-2 |
CY28341-2
Document #: 38-07471 Rev. *B
Page 12 of 19
Power-down Deassertion (K7 Mode):
When deasserted PD# to high level, all clocks are enabled and
start running on the rising edge of the next full period in order
to guarantee a glitch-free operation, no partial clock pulses.
Note:
3.
This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device
is not affected, VTT_PWRGD# is ignored.
PCI 33MHz
PW RDW N#
CPU 133MHz
CPU# 133MHz
AGP 66MHz
REF 14.318MHz
USB 48MHz
<1.5 msec
SDRAM 133MHz
DDRT 133MHz
DDRC 133MHz
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_GD#
Sample Sels
Off
Off
On
On
State 1
(Note A)
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)
[3]
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY28341-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk |
| CY28341OC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28341OC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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