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參數(shù)資料
| 型號(hào)： | CY29962 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，150兆赫多輸出零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 91K |
| 代理商： | CY29962 |
2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer
CY29962
Cypress Semiconductor Corporation
Document #: 38-07364 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
62
Features
2.5V or 3.3V operation
Output frequency up to 150MHz
Supports PowerPC
and Pentium
processors
21 clock outputs: drive up to 42 clock lines
LVPECL or LVCMOS/LVTTL clock input
Output-to-output skew < 150 ps
Table 1. Frequency Table
[1]
Split 2.5V/3.3V outputs
Spread-spectrum-compatible
Glitch-free output clocks transitioning
Output disable control
Pin-compatible with MPC9600
Industrial temperature range:
–
40
°
C to +85
°
C
48-pin TQFP package
Note:
1.
Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1) or 25 MHz to 50 MHz (FB_SEL = 0).
SELA
0
1
QA
VCO/2
VCO/4
SELB
0
1
QB
VCO/2
VCO/4
SELC
0
1
QC
VCO/2
VCO/4
FB_SEL
0
1
FB_OUT
VCO/8
VCO/12
Block Diagram
Pin Configuration
/2
/4
/8
/12
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
SELC
FB_SEL
OE#
FB_OUT
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
D Q
D Q
D Q
D Q
0
1
0
1
0
1
0
1
FB
C
B
A
0
1
REF
FB
0
1
AVDD
PLL
CY29962
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
VSS
TCLK
PECL_CLK
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
SELA
SELB
SELC
VSSC
V
O
Q
Q
V
Q
Q
V
Q
Q
Q
V
V
F
Q
Q
V
Q
Q
V
Q
Q
Q
V
VSSA
FB_OUT
QB0
QB1
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
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