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參數(shù)資料
| 型號： | CY29962 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，150兆赫多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 91K |
| 代理商： | CY29962 |
CY29962
Document #: 38-07364 Rev. *B
Page 4 of 7
Maximum Ratings
[3]
Maximum Input Voltage Relative to V
SS
:............. V
SS
–
0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................
–
65
°
C to + 150
°
C
Operating Temperature:................................
–
40
°
C to +85
°
C
Maximum ESD protection...............................................2 kV
Maximum Power Supply:................................................5.5V
Maximum Input Current:
..................................................±
20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Table 3. DC Parameters
V
DD
= 2.5V ±5%, T
A
=
–
40
°
C to +85
°
C
Parameter
V
IL[4]
V
IH[4]
V
PP
V
CMR[5]
I
IL[6]
I
IH[6]
V
OL[7]
V
OH[7]
I
DD
C
IN
Description
Conditions
Min.
V
SS
1.7
500
Typ.
Max.
0.7
V
DD
1000
V
DD
–
0.6
–
120
120
0.6
Unit
V
V
mV
V
μA
μA
V
V
mA
pF
Input LOW Voltage
Input HIGH Voltage
Peak-to-Peak Input Voltage PECL_CLK
Common Mode Range PECL_CLK
Input LOW Current (@ V
IL
= V
SS
)
Input HIGH Current (@ V
IH
= V
DD
)
Output LOW Voltage
Output HIGH Voltage
Quiescent Supply Current
Input Pin Capacitance
V
DD
–
1.4
I
OL
= 15 mA
I
OH
=
–
15 mA
V
DD
and AV
DD
1.8
10
4
13
Table 4. DC Parameters
V
DD
= 3.3V ±5%, T
A
=
–
40
°
C to +85
°
C
Parameter
V
IL[3]
V
IH[3]
V
PP
V
CMR[5]
I
IL[6]
I
IH[6]
V
OL[7]
V
OH[7]
I
DD
C
IN
Notes:
3.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
The LVCMOS inputs threshold is at 30% of V
.
5.
The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR
range and the input lies within the V
specification.
6.
Inputs have pull-up/pull-down resistors that affect input current.
7.
Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines.
Description
Conditions
Min.
V
SS
2.0
500
Typ.
Max.
0.8
V
DD
1000
V
DD
–
0.6
–
120
120
0.55
Unit
V
V
mV
V
μA
μA
V
V
mA
pF
Input LOW Voltage
Input HIGH Voltage
Peak-to-Peak Input Voltage PECL_CLK
Common Mode Range PECL_CLK
Input LOW Current (@ V
IL
= V
SS
)
Input HIGH Current (@ V
IH
= V
DD
)
Output LOW Voltage
Output HIGH Voltage
Quiescent Supply Current
Input Pin Capacitance
V
DD
–
1.4
I
OL
= 24mA
I
OH
=
–
24mA
V
DD
and AV
DD
2.4
15
4
20
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