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參數(shù)資料
| 型號(hào)： | CY29962 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，150兆赫多輸出零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | CY29962 |
CY29962
Document #: 38-07364 Rev. *B
Page 2 of 7
Pin Description
[2]
Pin
Name
PWR
I/O
I, PD PECL clock input
I, PU PECL clock input
I, PD External reference/test clock input
Clock Outputs
. See
Table 1
for frequency selections.
Description
3
4
2
38, 39, 40, 42,
43, 45, 46
26, 27, 28, 30,
31, 33, 34
15, 16, 18, 19,
21, 22, 23
35
PECL_CLK
PECL_CLK#
TCLK
QA(6:0)
VDDA
O
QB(6:0)
VDDB
O
Clock Outputs
. See
Table 1
for frequency selections.
QC(6:0)
VDDC
O
Clock Outputs
. See
Table 1
for frequency selections.
FB_OUT
VDD
O
Feedback Clock Output
. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL; see
Table 1
. A bypass delay
capacitor at this output will control Input Reference/ Output Banks phase
relationships.
Frequency Select Inputs
. These inputs select the divider ratio at
QA(0:6) outputs. See
Table 1
.
Frequency Select Inputs
. These inputs select the divider ratio at
QB(0:6) outputs. See
Table 1
.
Frequency Select Inputs
. These inputs select the divider ratio at
QC(0:6) outputs. See
Table 1
.
Feedback Select Inputs
. These inputs select the divide ratio at FB_OUT
output. See
Table 1
.
I, PD
Feedback Clock Input
. Connect to FB_OUT for accessing the PLL.
Reference Select Input
. When HIGH, the PECL clock is selected. When
LOW, TCLK is the reference clock.
Output Enable Input
. When asserted LOW, enables all of the outputs.
When pulled HIGH, disables to high impedance all of the outputs except
FB_OUT.
Power supply for Bank A clock buffers
Power supply for Bank B clock buffers
Power supply for Bank C clock buffers
Power supply for core
Power Supply for PLL
. When AVDD is set LOW, PLL is bypassed.
Common ground for Bank A
Common ground for Bank B
Common ground for Bank C
Common ground
9
SELA
I, PU
10
SELB
I, PU
11
SELC
I, PU
7
FB_SEL
I, PU
47
6
FB_IN
REF_SEL
I, PU
14
OE#
I, PD
37, 44
25, 32
13, 20
5
8
36, 41
24, 29
12, 17
1, 48
VDDA
VDDB
VDDC
VDD
AVDD
VSSA
VSSB
VSSC
VSS
Table 2. Function Table
Control Pin
0
1
REF_SEL
AVDD
OE#
SELA
SELB
SELC
FB_SEL
TCLK
PLL Bypass, outputs controlled by OE#
Outputs Enabled
Output Bank A at VCO/2
Output Bank B at VCO/2
Output Bank C at VCO/2
Feedback Output at VCO/8
PECL_CLK
PLL power
Outputs Disabled (except FB_OUT)
Output Bank A at VCO/4
Output Bank B at VCO/4
Output Bank C at VCO/4
Feedback Output at VCO/12
Note:
2.
A bypass capacitor (0.1
μ
”
). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
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