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參數(shù)資料
| 型號(hào)： | CY29962 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，150兆赫多輸出零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 91K |
| 代理商： | CY29962 |
CY29962
Document #: 38-07364 Rev. *B
Page 5 of 7
Table 5. AC Parameters
V
DD
= 3.3V ±5% or 2.5V ±5%, T
A
=
–
40
°
C to +85
°
C
[8]
Parameter
Description
Fref
Reference Input Frequency
Conditions
Min.
16
25
25
200
Typ.
Max.
33
50
75
400
10
Unit
MHz
FB_SEL = 1
FB_SEL = 0
FrefDC
Fvco
Tlock
Tr/Tf
Reference Input Duty Cycle
PLL VCO Lock Range
Maximum PLL lock Time
Output Clocks Rise/Fall Time
[9,10]
%
MHz
ms
0.55V to 2.0V, V
DD
= 3.3V
0.5V to 1.8V, V
DD
=2.5V
Q (
÷
2)
Q (
÷
4)
0.1
1.0
ns
Fout
Maximum Output Frequency
100
50
45
150
100
55
MHz
FoutDC
tpZL, tpZH
Output Duty Cycle
[9,10]
Output Enable Time
[9]
(all outputs)
Output Disable Time
[9]
(all outputs)
Cycle-to-Cycle Jitter
[9,10]
Any Output to Any Output Skew
[9,10]
50
%
2
10
ns
tpLZ, tpHZ
2
8
ns
TCCJ
Tskew
±100
ps
ps
Same Frequency
Different Frequency
Banks at different voltages
150
300
400
450
200
225
Tskew
Tskew(pp)
Tpd
Bank to Bank Skew
Part to Part Skew
[11]
Phase Error
[9,10]
ps
ps
ps
TCLK or PECL_CLK
to FB_IN
VDD = 3.3V
VDD = 2.5V
0
100
125
25
Notes:
8.
9.
10. 50
transmission line terminated into V
/2
11.
Part-to-part skew at a given temperature and voltage.
Parameters are guaranteed by design and characterization. Not 100% tested in production.
Ordering Information
Part Number
CY29962AI
CY29962AIT
Package Type
48-pin TQFP
48-pin TQFP - Tape and Reel
Production Flow
Industrial,
–
40
°
C to +85
°
C
Industrial,
–
40
°
C to +85
°
C
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