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參數(shù)資料
| 型號： | CY28341-2 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
| 中文描述： | 通用時(shí)鐘芯片的威盛P4M/KT/KM400的DDR系統(tǒng) |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 174K |
| 代理商： | CY28341-2 |
CY28341-2
Document #: 38-07471 Rev. *B
Page 14 of 19
Note:
4.
Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
length transmission line should be added to the other signal of the pair (e.g., AGP).
Table 11. Lumped Test Load Configuration
Component
0.7V Amplitude Value
1.0V Amplitude Value
R
tA1
, R
tA2
R
LA1
, R
LA2
T
PCB
R
LB1
, R
LB2
R
D
R
tB1
, R
tB2
C
LA
, C
LB
R
ref
33
49.9
3” 50
Z
∞
∞
0
2 pF
475
w/mult0 = 1
0
∞
3” 50
Z
63
470
33
2 pF
221
w/mult0 = 0
Group Timing Relationships and Tolerances
[4]
Offset (ps)
750
1,250
10ns
Tolerance (ps)
500
500
20ns
Conditions
CPUCS Leads
AGP Leads
30ns
t
CSAGP
t
AP
CPUCS to AGP
AGP to PCI
0ns
CLK Measurement Point
R
ref
R
tA1
CPUT
MULTSEL
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
CPUT#
Figure 10. P4 Load Termination
AGP CLOCK 66.6MHz
PCI CLOCK 33.3MHz
CPU CLOCK 66.6MHz
CPU CLOCK 100MHz
CPU CLOCK 133.3MHz
t
AP
t
CSAGP
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk |
| CY28341OC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28341OC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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