參數(shù)資料
型號： CXD3068Q
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo(CD數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)）)
中文描述： CD數(shù)字信號處理器具有內(nèi)置的數(shù)字式伺服（光盤數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)））
文件頁數(shù)： 90/135頁
文件大小： 1259K
代理商： CXD3068Q
– 90 –
CXD3068Q
§ 5-4. E:F Balance Adjustment Function (See Fig. 5-3.)
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to "0".
Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the
TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.)
§ 5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 5-3.)
When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9
to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing
Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to
FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this
time, SENS goes to high and the counter stop can be monitored.
Here, assume the FBIAS setting value FB9 to
FB1 and the FBIAS LIMIT value FBL9 to FBL1
are set in status A. For example, if command
registers FBUP = 0, FBV1 = 0, FBV0 = 0 and
FBSS = 1 are set from this status, down count
starts from status A and approaches the set
LIMIT value. When the LIMIT value is reached
and the FBIAS value matches FBL9 to FBL1,
the counter stops and the SENS pin goes to
high. Note that the up/down counter counts at
each sampling cycle of the focus servo filter.
The number of steps by which the count value
changes can be selected from 1, 2, 4 or 8 steps
by FBV1 and FBV0. When converted to FE
input, 1 step corresponds to 1/512
×
V
DD
×
0.4.
A
B
C
FBIAS setting value
(FB9 to FB1)
LIMIT value
(FBL9 to FBL1)
SENS pin
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
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