參數(shù)資料
型號: CXD3068Q
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo(CD數(shù)字信號處理器(內(nèi)置數(shù)字伺服系統(tǒng)))
中文描述: CD數(shù)字信號處理器具有內(nèi)置的數(shù)字式伺服(光盤數(shù)字信號處理器(內(nèi)置數(shù)字伺服系統(tǒng)))
文件頁數(shù): 11/135頁
文件大?。?/td> 1259K
代理商: CXD3068Q
– 11 –
CXD3068Q
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing .................................................................................................................... 12
§ 1-2. CPU Interface Command Table .................................................................................................... 12
§ 1-3. CPU Command Presets ................................................................................................................ 23
§ 1-4. Description of SENS Signals......................................................................................................... 30
[2] Subcode Interface
§ 2-1. P to W Subcode Readout.............................................................................................................. 57
§ 2-2. 80-bit Sub-Q Readout.................................................................................................................... 57
[3] Description of Modes
§ 3-1. CLV-N Mode.................................................................................................................................. 64
§ 3-2. CLV-W Mode................................................................................................................................. 64
§ 3-3. CAV-W Mode................................................................................................................................. 64
§ 3-4. VCO-C mode................................................................................................................................. 65
[4] Description of Other Functions
§ 4-1. Channel Clock Regeneration by Digital PLL Circuit ...................................................................... 68
§ 4-2. Frame Sync Protection.................................................................................................................. 70
§ 4-3. Error Correction............................................................................................................................. 70
§ 4-4. DA Interface................................................................................................................................... 71
§ 4-5. Digital Out...................................................................................................................................... 73
§ 4-6. Servo Auto Sequence.................................................................................................................... 74
§ 4-7. Digital CLV..................................................................................................................................... 82
§ 4-8. Playback Speed............................................................................................................................. 83
§ 4-9. Asymmetry Correction................................................................................................................... 84
§ 4-10. CD TEXT Data Demodulation ....................................................................................................... 85
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System.............................................................. 87
§ 5-2. Digital Servo Block Master Clock (MCK)....................................................................................... 88
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ....................................................... 89
§ 5-4. E: F Balance Adjustment Function ................................................................................................ 90
§ 5-5. FCS Bias Adjustment Function...................................................................................................... 90
§ 5-6. AGCNTL Function ......................................................................................................................... 92
§ 5-7. FCS Servo and FCS Search ......................................................................................................... 94
§ 5-8. TRK and SLD Servo Control ......................................................................................................... 95
§ 5-9. MIRR and DFCT Signal Generation.............................................................................................. 96
§ 5-10. DFCT Countermeasure Circuit...................................................................................................... 97
§ 5-11. Anti-Shock Circuit.......................................................................................................................... 97
§ 5-12. Brake Circuit.................................................................................................................................. 98
§ 5-13. COUT Signal ................................................................................................................................. 99
§ 5-14. Serial Readout Circuit.................................................................................................................... 99
§ 5-15. Writing to Coefficient RAM ............................................................................................................ 100
§ 5-16. PWM Output.................................................................................................................................. 100
§ 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 101
§ 5-18. Description of Commands and Data Sets ..................................................................................... 101
§ 5-19. List of Servo Filter Coefficients...................................................................................................... 124
§ 5-20. Filter Composition.......................................................................................................................... 126
§ 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 132
[6] Application Circuit
.................................................................................................................................. 133
Explanation of abbreviations AVRG:
Average
Auto gain control
Focus
Tracking
Sled
Defect
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
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