參數(shù)資料
型號： CXD3068Q
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo(CD數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)）)
中文描述： CD數(shù)字信號處理器具有內(nèi)置的數(shù)字式伺服（光盤數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)））
文件頁數(shù)： 101/135頁
文件大?。?/td> 1259K
代理商： CXD3068Q
– 101 –
CXD3068Q
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
PGFS1 PGFS0 PFOK1 PFOK0
0
0
0
MRS MRT1 MRT0
0
0
When D15 = 0.
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
§ 5-18. Description of Commands and Data Sets
$34
$348 (preset: $348 000)
PGFS1
0
0
1
1
0
1
0
1
High when the frame sync is of the correct timing,
low when not the correct timing.
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 2ms or longer.
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 4ms or longer.
High when the frame sync is the correct timing,
low when continuously not the correct timing for 8ms or longer.
PGFS0
Processing
These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed.
PFOK1
0
0
1
1
0
1
0
1
High when the RFDC value is higher than the FOK slice level,
low when lower than the FOK slice level.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 4.35ms or more.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 10.16ms or more.
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 21.77ms or more.
PFOK0
Processing
These commands set the FOK hold time. See $3B for the FOK slice level.
These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.
§ 5-17. Servo Status Changes Produced by LOCK Signal
When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
MRS: Switches the time constant for the MIRR comparator level generation of the MIRR generation circuit.
When MRS = 0, the time constant is set to normal. (default)
When MRS = 1, the time constant is delayed compared to the normal state.
The duration of MIRR = high, which is caused by the affection of the RFDC signal pulse-formed noise
and the like, is suppressed by setting MRS to 1.
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