參數(shù)資料
型號： CXD3068Q
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo(CD數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)）)
中文描述： CD數(shù)字信號處理器具有內(nèi)置的數(shù)字式伺服（光盤數(shù)字信號處理器（內(nèi)置數(shù)字伺服系統(tǒng)））
文件頁數(shù)： 121/135頁
文件大?。?/td> 1259K
代理商： CXD3068Q
– 121 –
CXD3068Q
$3F (preset: $3F 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
ASFG FTQ
1
0
0
AGHF ASOT
XT4D, XT2D:
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated. See the description of $3E for XT1D. Also, see the decription of "§5-2. Digital
Servo Block Master Clock (MCK)".
AGG4:
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is
as shown in the table below.
AGG4
0
1
AGGF
0
1
—
—
0
0
1
1
AGGT
—
—
0
1
0
1
0
1
FE input
conversion
1/36
×
V
DD
/2
1/16
×
V
DD
/2
—
—
TE input
conversion
—
—
1/16
×
V
DD
/2
1/8
×
V
DD
/2
See $37 for AGGF and AGGT.
The presets are AGG4 = 0,
AGGF = 1 and AGGT = 1.
: preset, —: don't care
XT1D
0
1
0
0
XT2D
0
—
1
0
XT4D
0
—
—
1
According to XTSL
1/1
1/2
1/4
Frequency division ratio
Sine wave amplitude
1/64
×
V
DD
/2
1/32
×
V
DD
/2
1/16
×
V
DD
/2
1/8
×
V
DD
/2
: preset, —: don't care
DRR2 to DRR0
: Partially clears the Data RAM values (0 write).
The following values are cleared when 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note)
Set DRR1 and DRR0 on for 50μs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, the FCS servo filter
is forcibly set to gain normal status.
On when 1; default when 0
FTQ:
The slope of the output during focus search is 1/4 of the conventional output slope.
On when 1; default when 0 .
AGHF:
This halves the frequency of the internally generated sine wave during AGC.
ASOT:
The anti-shock signal, which is internally detected, is output from the ATSK pin.
Output when set to 1; default = 0
Vibration detection when a high signal is output for the anti-shock signal output.
相關(guān)PDF資料
PDF描述
CXD3152AR Signal Processor LSI for Single-chip CCD B/W Camera
CXD3400 6-channel CCD Vertical Clock Driver
CXD3400N Silver Mica Capacitor; Capacitance:30000pF; Capacitance Tolerance: 2%; Series:CD42; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:27mm; Leaded Process Compatible:No RoHS Compliant: No
CXD3410 Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
CXD3410GA Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD3141 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ccd-cmosIC資料
CXD3142R 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Signal Processor LSI for Single-Chip CCD Color Camera
CXD3152AR 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Signal Processor LSI for Single-chip CCD B/W Camera
CXD3152R 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Signal Processor LSI for Single-chip CCD B/W Camera
CXD3172AR 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Signal Processor LSI for Single CCD Color Camera
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*