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參數資料
| 型號： | CSP1027 |
| 元件分類： | Codec |
| 英文描述： | CSP1027 Voice Band Codec for Cellular Handset and Modem Applications |
| 中文描述： | CSP1027語音頻帶編解碼器的蜂窩手機和調制解調器應用 |
| 文件頁數： | 45/64頁 |
| 文件大?。?/td> | 937K |
| 代理商： | CSP1027 |
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Lucent Technologies Inc.
Data Sheet
December 1999
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
45
7 Application Information
(continued)
Thus, the contributions to frequency variation add up
as follows:
Initial Tolerance of Crystal
Temperature Tolerance of Crystal
Aging Tolerance of Crystal
Load Capacitor Variation
CSP1027 Circuit Variation
C
0
Variation
Board Variation
Total
10.0 ppm
25.0 ppm
6.0 ppm
4.7 ppm
15.5 ppm
7.8 ppm
23.3 ppm
92.3 ppm
This type of detailed analysis should be performed for
any crystal-based application where frequency accu-
racy is critical.
7.5 Programmable Clock Generation
Refer to Figure 17 on page 15 for the following discus-
sion.
The programmable clock divider is set by writing the
6-bit CDIV3 field of the
cioc2
register (see Table 9 on
page 28). The user can select an appropriate integer
value which sets the ratio of the CLK input clock to the
oversampling rate of the codec. The following examples
illustrate this feature.
7.5.1 Application Example 1
I
GSM application.
I
Input clock, CLK, rate: 26 MHz (38.46 ns).
I
Codec PCM rate required: 8 kHz (oversampling
rate = 1 MHz).
Solution:
I
CLK/CK
OS
= 26, so set CLK/ICLK0 = 1 and ICLK0/
CK
OS
to 26.
I
Set CDIV0 = 0 and CDIV3 = 26 (011010).
7.5.2 Application Example 2
I
IS-54 application.
I
Input clock, CLK, rate: 40 MHz (25.0 ns).
I
Codec PCM rate required: 8 kHz (oversampling
rate = 1 MHz).
Solution:
I
CLK/CK
OS
= 40, so set CLK/ICLK0 = 1 and ICLK0/
CK
OS
to 40.
I
Set CDIV0 = 0 and CDIV3 = 40 (101000).
7.5.3 Application Example 3
I
Modem data pump.
I
Codec sampling frequency required = 9.6 kHz
(instead of 8 kHz).
I
Need highest possible input clock, CLK, rate (allow-
able by the DSP).
Solution:
I
Codec oversampling rate = 9.6 kHz * 125 = 1.2 MHz.
I
Assuming a DSP16A or DSP1616 with
maximum rate of 40 MHz,
CLK = 39.6 MHz = 1.2 MHz x 33, so
CLK/ICLK0 = 1 and ICLK0/CK
OS
= 33.
I
Set CDIV0 = 0 and CDIV3 = 33 (100001).
I
Disable the high-pass filters (HPFE = 1) because the
–3 dB corner frequency is now too high
(270 Hz x 1.2 = 324 Hz).
I
Low-pass filter –3 dB corner frequency is now
4.08 kHz (= 3.4 kHz x 1.2). (Note that external DSP
software can provide additional postfiltering, if
desired.)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CSP1027J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Linear CODEC |
| CSP1027-J11-DB | 制造商:Alcatel-Lucent 功能描述: |
| CSP1027S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Linear CODEC |
| CSP1027-S11-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CSP1034AH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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