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| 型號： | CSP1027 |
| 元件分類： | Codec |
| 英文描述： | CSP1027 Voice Band Codec for Cellular Handset and Modem Applications |
| 中文描述： | CSP1027語音頻帶編解碼器的蜂窩手機和調(diào)制解調(diào)器應(yīng)用 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 937K |
| 代理商： | CSP1027 |
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CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
December 1999
Lucent Technologies Inc.
32
6 Signal Descriptions
(continued)
6.3.8 SADD
Serial Address:
When not in multiprocessor mode,
SADD is an input that selects between the codec data
registers,
cdx(D/A)
and
cdx(A/D)
, and codec control
registers,
cioc
[0:3]. SADD is inverted and latched on the
rising edge of IOCK and compared against a zero for
data and a one for control, to determine if input data on
DI is loaded from the input shift register (
isr
) into
cdx(D/A)
or one of
cioc
[0:3]. Once SADD indicates a
control word, the internal codec status flag appears on
DO, replacing
cdx(A/D)
. While not performing a serial
transmission, SADD low causes the internal codec sta-
tus flag to be output on DO.
In multiprocessor mode, SADD is an output when the
tdms
time slot dictates a serial output transmission; oth-
erwise, it is an input. While an output, SADD is the
inverted 8-bit serial transmit address output, LSB first.
SADD changes on the rising edges of IOCK. While an
input, SADD is inverted and latched on the rising edge
of IOCK and compared against the
cdx(D/A)
and
cioc
[0:3] serial receive addresses to determine if input
data on DI is loaded from the input shift register (
isr
) into
cdx(D/A)
or
cioc
.
6.4 External Gain Control Interface
The external gain control interface consists of one input.
6.4.1 EIGS
External Input Gain Select:
A logic low or no connect
selects the microphone preamplifier. A logic high selects
the single op amp input mode where external resistors
set the A/D input range. Note that EIGS is a digital pin
whose input levels are relative to digital power and
ground (V
DD
and V
SS
).
6.5 Digital Power and Ground
V
DD
Digital Power Supply:
3.0 V to 5.0 V supply.
V
SS
Digital Ground:
0 V.
6.6 Analog Interface
The analog interface consists of the two inputs, two out-
puts, a regulated output voltage reference, and a capac-
itor connection for the codec.
6.6.1 MICIN
Analog Input from Microphone:
Low-level analog sig-
nal from electret condenser microphone selected by
INSEL bit in codec control register,
cioc0
(see Table 7
on page 26).
6.6.2 AUXIN
Analog Input from Auxiliary:
When used in preampli-
fier mode (EIGS = 0), AUXIN is a low-level analog signal
selected by INSEL bit in codec control register,
cioc0
(see Table 7 on page 26). The characteristics of AUXIN
are identical to MICIN.
When used in external gain select mode (EIGS = 1),
AUXIN is the output of the inverting amplifier. The INSEL
bit has no effect in this mode.
6.6.3 AOUTP
Noninverting Analog Output:
In conjunction with
AOUTN, this output can drive a 2 k
load in differential
mode or a 1 k
load ac-coupled to analog ground.
6.6.4 AOUTN
Inverting Analog Output:
In conjunction with AOUTP,
this output can drive a 2 k
load in differential mode or a
1 k
load ac-coupled to ground.
6.6.5 V
REG
Regulated Output Voltage:
For electret condenser
microphone. Vout = 3 V ± 10%, Iout = 250 μA max. A
1 μF and 0.1 μF ceramic type X7R capacitor to ground
must be provided at this pin (see Figure 28 on page 34).
6.6.6 REFC
External Capacitor Connection:
Internal voltage regu-
lator bypassing. A 0.22 μF ceramic type X7R capacitor
to ground must be provided at this pin.
6.7 Analog Power and Ground
V
DDA
Analog Power Supply:
5.0 V supply.
V
SSA
Analog Ground:
0 V.
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