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參數(shù)資料
| 型號(hào)： | CS8420-DSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 83/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1729 |
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84
DS245F4
CS8420
15.1.5
One-Byte Mode
In many applications, the channel status blocks for the A and B channels will be identical. In this situation,
if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will
be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the
same byte to the other block. One-Byte mode takes advantage of the often identical nature of A and B
channel status data.
When reading data in one-byte mode, a single byte is returned, which can be from channel A or B data,
depending on a register control bit. If a write is being done, the CS8420 expects a single byte to be input
to its control port. This byte will be written to both the A and B locations in the addressed word.
One-Byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes’
worth of information in 1 byte's worth of access time. If the control port's auto-increment addressing is
used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done
especially efficiently.
15.1.6
Two-Byte Mode
There are those applications in which the A and B channel status blocks will not be the same, and the
user is interested in accessing both blocks. In these situations, Two-Byte mode should be used to access
the E buffer.
In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out will
represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is
similar, in that two bytes must now be input to the CS8420's control port. The A channel status data is
first, B channel status data second.
15.2
AES3 User (U) Bit Management
The CS8420 U bit manager has four operating modes:
Mode 1. Transmit all zeros
Mode 2. Block mode
Mode 3. Reserved
Mode 4. IEC Consumer B
15.2.1
Mode 1: Transmit All Zeros
Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U data
embedded in an input AES3 data stream. This mode is intended for the user who does not want to trans-
ceive U data, and simply wants the output U channel to contain no data.
15.2.2
Mode 2: Block Mode
Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered from
input to output, using a cascade of three block-sized RAMs to perform the buffering. The user has access
to the second of these three buffers, denoted the E buffer, via the control port. Block mode is designed
for use in AES3 in, AES3 out situations in which input U data is decoded using a microcontroller via the
control port. It is also the only mode in which the user can merge his/her own U data into the transmitted
AES3 data stream.
The U buffer access only operates in Two-Byte mode, since there is no concept of A and B blocks for user
data. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first
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| CS8420-DSZR | 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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