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參數(shù)資料
| 型號： | CS8420-DSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 43/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1729 |
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48
DS245F4
CS8420
11. SYSTEM AND APPLICATIONS ISSUES
11.1
Reset, Power Down and Start-up Options
When RST is low, the CS8420 enters a low-power mode. All internal states are reset, including the control
port and registers, and the outputs are muted. When RST is high, the control port becomes operational, and
the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause
the part to leave the low-power state and begin operation. After the PLL and the SRC have settled, the AES3
and serial audio outputs will be enabled.
Some options within the CS8420 are controlled by a start-up mechanism. During the reset state, some of
the output pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level
of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be
used to set alternative modes in the CS8420 by connecting a 47 k
Ω resistor between the pin and either VD+
(High) or DGND (Low). For each mode, every start-up option select pin MUST have an external pull-up or
pull-down resistor. In software mode, the only start-up option pin is EMPH, which is used to set a chip ad-
dress bit for the control port in IC mode. Hardware modes use many start-up options, which are detailed in
the hardware definition section at the end of this data sheet.
11.2
Transmitter Startup
When the CS8420 is taken out of power-down and the AES3 receiver is configured to be in-circuit, the part
uses the clock recovered from the AES3 input stream to advance its internal state machine to run. This can
be a problem if no valid AES3 stream is present at the RXP/RXN pins and data input through the serial audio
port needs to be output through the AES3 transmitter.
To complete initialization and begin operation when the AES3 receiver is in-circuit and no valid AES3 input
stream is presented to the RXP/RXN pins, the user must execute the following sequence:
1.
Place the CS8420 in power-down (RUN = 0).
2.
Set the serial audio input and output ports to Slave mode (SIMS = 0, SOMS = 0).
3.
Set the input and output time base to the OMCK input pin (OUTC = 0, INC = 1).
4.
Configure the SRC to receive its input from the serial audio input port (SRCD = 0).
5.
Configure the serial audio output port to receive its input from the serial audio input port (SPD[1:0] = 01).
6.
Configure the AES3 transmitter to receive its input from the serial audio input port (TXD[1:0] = 01).
7.
Set the RUN bit (RUN = 1).
After completing steps 1-7, the transmitter will function properly, and the data flow can be altered for the
application without powering down.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8420-DSZR | 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| CS8421 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
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