參數(shù)資料
型號: CS8420-DSZ
廠商: Cirrus Logic Inc
文件頁數(shù): 33/94頁
文件大?。?/td> 0K
描述: IC CONV S/R DGTL AUDIO 28-SOIC
標準包裝: 27
類型: 采樣率轉換器
應用: 數(shù)字音頻
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 28-SOIC
包裝: 管件
產品目錄頁面: 759 (CN2011-ZH PDF)
其它名稱: 598-1729
DS245F4
39
CS8420
10.7
Serial Audio Output Port Data Format (06h)
SOMS
Master/Slave Mode Selector
0 - Serial audio output port is in Slave mode (default)
1 - Serial audio output port is in Master mode
SOSF
OSCLK frequency (for Master mode)
0 - 64*Fso (default)
1 - 128*Fso
SORES[1:0]
Resolution of the output data on SDOUT and AES3 output when the sample rate converter is
set as the source
00 - 24 bit resolution (default)
01 - 20 bit resolution
10 - 16 bit resolution
11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and
V bits, the time slot normally occupied by the P bit is used to indicate the location
of the block start, SDOUT pin only, serial audio output port clock must be derived
from the AES3 receiver recovered clock)
SOJUST
Justification of SDOUT data relative to OLRCK
0 - Left-Justified (default)
1 - Right-Justified (Master mode only)
SODEL
Delay of SDOUT data relative to OLRCK, for left-justified data formats
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
(default)
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
SOSPOL
OSCLK clock polarity
0 - SDOUT transitions occur on falling edges of OSCLK (default)
1 - SDOUT transitions occur on rising edges of OSCLK
SOLRPOL
OLRCK clock polarity
0 - SDOUT data is for the left channel when OLRCK is high (default)
1 - SDOUT data is for the right channel when OLRCK is high
7
6
5
4
3210
SOMS
SOSF
SORES1
SORES0
SOJUST
SODEL
SOSPOL
SOLRPOL
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相關代理商/技術參數(shù)
參數(shù)描述
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