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參數(shù)資料
| 型號： | CS8420-DSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 24/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1729 |
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30
DS245F4
CS8420
9.
CONTROL PORT DESCRIPTION AND TIMING
The control port is used to access the registers, allowing the CS8420 to be configured for the desired operational
modes and formats. In addition, Channel Status and User data may be read and written via the control port. The
operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to
avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port has two modes: SPI and IC, with the CS8420 acting as a slave device. SPI mode is selected if
there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. IC mode is selected
by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.
9.1
SPI Mode
In SPI mode, CS is the CS8420 chip select signal. CCLK is the control port bit clock (input into the CS8420
from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line
to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 22 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first
7 bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator (R/W),
which should be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the
address of the register that is to be updated. The next 8 bits are the data which will be placed into the register
designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled
high or low with a 47 k
Ω resistor, if desired.
There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
then the MAP will stay constant for successive read or writes. If INCR is set to a 1, then the MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not,
as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high-
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively.
MA P
MSB
LSB
DATA
by te 1
by te n
R/W
AD D R ESS
CH IP
ADDRESS
CH IP
CD IN
CC L K
CS
CD O U T
MSB
LSB MSB
LSB
0010000
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 22. Control Port Timing in SPI Mode
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8420-DSZR | 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| CS8421 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
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