參數(shù)資料
型號(hào)： CS8420-DSZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 40/94頁(yè)
文件大小： 0K
描述： IC CONV S/R DGTL AUDIO 28-SOIC
標(biāo)準(zhǔn)包裝： 27
類型： 采樣率轉(zhuǎn)換器
應(yīng)用： 數(shù)字音頻
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC
包裝： 管件
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
其它名稱： 598-1729
DS245F4
45
CS8420
10.16 Receiver Error Mask (11h)
The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis-
ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will
appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and
will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set
to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver
error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect
the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they
do not affect the current audio sample even when unmasked. This register defaults to 00.
10.17 Channel Status Data Buffer Control (12h)
BSEL
Selects the data buffer register addresses to contain User data or Channel Status data
0 - Data buffer address space contains Channel Status data (default)
1 - Data buffer address space contains User data
CBMR
Control for the first 5 bytes of channel status “E” buffer
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
(default)
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
DETCI
D to E C-data buffer transfer inhibit bit.
0 - Allow C-data D to E buffer transfers (default)
1 - Inhibit C-data D to E buffer transfers
EFTCI
E to F C-data buffer transfer inhibit bit.
0 - Allow C-data E to F buffer transfers (default)
1 - Inhibit C-data E to F buffer transfers
CAM
C-data buffer control port access mode bit
0 - One byte mode
1 - Two byte mode
CHS
Channel select bit
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
1 - Channel B information is displayed at the EMPH pin and in the receiver channel
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
76543210
0
QCRCM
CCRCM
UNLOCKM
VM
CONFM
BIPM
PARM
76543210
0
BSEL
CBMR
DETCI
EFTCI
CAM
CHS
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參數(shù)描述
CS8420-DSZR 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
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CS8421_06 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter
CS8421_09 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter
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